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VLSI array processor implementation of quasi-block state-space IIR digital filters
, H. Abdelhameed
Published in IEEE, Piscataway, NJ, United States
A new array processor implementation of IIR digital filter is proposed with high input sampling rate which is not limited by the speed of the processor elements involved. The proposed implementation is based on the quasi-block state-space description of IIR digital filter corresponding to the case of parallel combination of second-order sections. Performance comparison (in terms of hardware complexity and speed) of the proposed implementation with another existing implementation is also presented.
About the journal
JournalData powered by TypesetProceedings of the Fifteenth National Radio Science Conference. NRSC '98 (Cat. No.98EX109)
PublisherData powered by TypesetIEEE, Piscataway, NJ, United States
Open AccessNo