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Two-stage interface circuit design for a 32-color resolution optical sensor
, Yohannes I., Bermak A.
Published in
Volume: 13
Issue: 2
Pages: 610 - 617
An interface circuit design for an optical sensor based on a two-stage cascaded architecture is presented in this paper. The proposed design is a mixed signal solution that provides few advantages in terms of speed, power consumption, higher resolution with smaller number of storage units, and small area for future on-chip integration. Simulation and experimental results for five bits resolution (32 levels) are presented to validate the design. We are aiming for a single-chip integrated solution; however, for a quick proof of concept, the proposed design has been implemented as a PCB using discrete off-the-shelf components. The biasing current and power consumption from the PCB implementation are 192 mA and 1.3 W, respectively, at a 6.75-V supply voltage. © 2001-2012 IEEE.
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JournalIEEE Sensors Journal
Open AccessNo