The performance of FinFET-based FPGA cluster is evaluated with technology scaling for channel length from 20nm down to 7nm showing the scaling trends of basic performance metrics. The impact of threshold voltage variation, considering die-to-die variations, on the delay, power, and power-delay product is reported after the simulation of a 2-bit adder benchmark. Simulation results show an increasing trend of the average power and power-delay product variations with threshold voltage as we go down with technology node. On the contrary, the delay is showing the least percentage of variations with threshold voltage at the most advanced node of 7nm. © 2015 IEEE.