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Mapping 3-D IIR digital filter onto systolic arrays
Published in Springer Netherlands
1996
Volume: 7
   
Issue: 1
Pages: 7 - 26
Abstract
We present here an efficient systolic implementation for 3-D IIR digital filters. The systolic implementation is obtained by using an algebraic mapping technique. This new mapping technique gives us the choice to mix pipelined variables and broadcast variables. We also determine, through the mapping method, the buffer sizes, the direction of variables propagations and the data feeding and extracting points. The resultant systolic array implementation is a modular structure composed of 2-D filter modules connected by simple buffers. This new systolic implementation is regular, modular and amenable to VLSI Implementation. © 1996 Kluwer Academic Publishers.
About the journal
JournalData powered by TypesetMultidimensional Systems and Signal Processing
PublisherData powered by TypesetSpringer Netherlands
ISSN09236082
Open AccessNo