Published in Publ by IEEE, Piscataway, NJ, United States
Pages: 1971 - 1974
This paper gives a new architecture that can support wavelet analysis in both compression and dilation. Its efficiency allows processing at speeds of up to one input sample per clock cycle without buffering. Therefore, it can generate several wavelet coefficients at the same time. This architecture is fully parallel and it can easily be adapted to user requirements by specifying some constraints at compile time during a synthesis process.