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FPGA Implementation of a Sub-pixel Correction Algorithm for Active Laser Range Finders.

, Yvon savaria
Published in
Pages: 604 - 606

This paper presents a FPGA implementation of a Sub-pixel correction algorithm for active laser range finders. It shows how to replace complex CPU operations by an efficient use of arithmetic functional units and lookup tables LUTs. This leads to a less complex architecture and an increase in performance. The architecture of a processor element, its complexity and performance on a Xilinx FPGA device are presented.

About the journal
JournalIAPR Workshop on Machine Vision Application
Open AccessYes