FPGA Implementation of a Sub-pixel Correction Algorithm for Active Laser Range Finders.
This paper presents a FPGA implementation of a Sub-pixel correction algorithm for active laser range finders. It shows how to replace complex CPU operations by an efficient use of arithmetic functional units and lookup tables LUTs. This leads to a less complex architecture and an increase in performance. The architecture of a processor element, its complexity and performance on a Xilinx FPGA device are presented.
|Journal||IAPR Workshop on Machine Vision Application|