A framework is presented for the prediction and estimation of the design yield of VLSI systems through design refinement steps. The design yield is calculated from simple analytical formulas and provides an effective early-warning tool for the logic designer that can be used to eliminate the necessity of running simulation programs for different versions of a given design. A number of metrics that are useful during the design process are introduced. These metrics can be included into a set of CAD tools. Test cost minimization is proposed as a possible application of this approach. Finally, a small example is developed to demonstrate that this approach is practical.