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Design and modeling of low-power clockless serial link for data communication systems
Alser M.H.,
Published in IEEE
2011
Abstract
Due to the continuing progress in integrated circuit technology, SoC (system-on-chip) is becoming larger requiring many long on-chip wires that interconnect SoC's modules. However, it is becoming increasingly challenging to synchronously and reliably communicate synchronous data between high-speed modules. Therefore, to take advantage of the increased module's processing speed available and to improve the overall system performance requires high-speed communication networks. This paper overviews the problems and limitations associated with the use of multi-bit conventional bus as a medium of synchronous communication in today's multi-module based SoC and presents an asynchronous serial link as a potential high-performance alternative solution. Furthermore, it reviews the current state-of-the-art of serial links and proposes a new architecture based on quarter-rate concept that will eventually lead to the implementation of a low-power and high-speed intermodule link in SoC. © 2011 IEEE.
About the journal
JournalData powered by Typeset2011 National Postgraduate Conference - Energy and Sustainability: Exploring the Innovative Minds, NPC 2011
PublisherData powered by TypesetIEEE
Open AccessNo