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Analysis and optimization for dynamic read stability in 28nm SRAM bitcells
Elthakeb A.T., Haine T., Flandre D., , , Bol D.
Published in Institute of Electrical and Electronics Engineers Inc.
2015
Volume: 2015-July
   
Pages: 1414 - 1417
Abstract
The importance of the dynamic analysis for SRAM operation increases as a result of shrinking access cycle time, voltage scaling and increased process variations. In this paper, quantitative study of the dynamic read noise margin (DNM) is introduced showing the evolution from the static read noise margin (SNM) to DNM through cumulative dynamic effects in 28nm FDSOI. The impact of parasitic capacitances on the DNM is further analyzed. Finally, we show that by sizing for a 150-mV DNM instead of a 150-mV SNM and by inserting two 0.5fF extra caps in the bitcell allows reducing the pull-down NMOS width by a factor 3.5×. © 2015 IEEE.
About the journal
JournalData powered by TypesetProceedings - IEEE International Symposium on Circuits and Systems
PublisherData powered by TypesetInstitute of Electrical and Electronics Engineers Inc.
ISSN02714310
Open AccessNo