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A VLSI architecture of 2D wavelet transformsPublished in
2000
Volume: 1
Pages: 370 - 373
This paper presents a new implementation of a 2D wavelet transform in a VLSI circuit, for real-time digital signal processing. The parallel algorithm of the 2D wavelet transform (2D-WT) used for designing and implementing this new architecture enhances the performance of computations. The proposed multi-elementary processor architecture of 2D-WT yields a very flexible hardware configuration. This approach offers a high processing speed, relative to other methods, for providing the wavelet coefficients. The 2D-WT is a powerful tool for several applications, the most important one being image processing. © 2000 IEEE.
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About the journal
| Journal | Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems |
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Authors (1)
Jean Louis Houle- Ajman University
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