This paper presents an only hardware description language (HDL)-based serial link (SerDes) design that has been synthesized on Altera DE2-70 FPGA board as a quick proof of concept for validation purpose. Though some blocks are adopted from their analog counterpart however the entire architecture has been implemented using the Verilog language, hence requires no analog or off-chip components and exhibit better power efficiency and jitter but lower data rate. Furthermore, being an HDL-based design makes it easy to implement as an IC and suitable for certain applications such as multicore and NoC architectures. Key circuit blocks include a built-in PRBS generator for testing purpose, a clock generation circuit, and a quarter-rate clock and data recovery (CDR) circuit. Including FPGA's peripherals, the proposed link achieves a power efficiency of 5.79 pW/b/s and a bit error rate (BER) lower than 10-12, and operates continuously over the range of 167.32 Mb/s to 193.6 Mb/s. © 2017 IEEE.