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A protection mechanism for Intellectual Property Rights (IPR) in FPGA design environment
W. Adi, B. Soudan,
Published in Institute of Electrical and Electronics Engineers (IEEE)
2003
Volume: 1
   
Pages: 92 - 95
Abstract
One of the major difficulties in offering new VLSI designs is protecting the designer's Intellectual Property Rights IRP. It often requires limited field deployment and testing before a novel implementation may be accepted for general use. The difficulty arises in the need to deploy the design for testing while disabling the tester from deciphering the design details. A similar requirement applies when the designer is interested in limiting the number of deployments as part of a business agreement. This work leverages the similarities between the issues of IPR protection in the hardware and software arenas and presents a novel solution to protect the use of designs in FPGA hardware environment. The mechanisms used are based on hardware-supported design encryption and secured authentication protocols. © 2003 IEEE.
Concepts (15)
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    Protection
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    Intellectual property
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    Field programmable gate arrays
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    Manufacturing
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    Testing
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    Hardware
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    Authentication
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    Very large scale integration
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    Programming profession
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    Educational institutions
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    Fpga device uniqueness
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    Global authentication
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    Provable identification
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    Secured ipr
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    Vlsi identity