One of the major difficulties in offering new VLSI designs is protecting the designer's Intellectual Property Rights IRP. It often requires limited field deployment and testing before a novel implementation may be accepted for general use. The difficulty arises in the need to deploy the design for testing while disabling the tester from deciphering the design details. A similar requirement applies when the designer is interested in limiting the number of deployments as part of a business agreement. This work leverages the similarities between the issues of IPR protection in the hardware and software arenas and presents a novel solution to protect the use of designs in FPGA hardware environment. The mechanisms used are based on hardware-supported design encryption and secured authentication protocols. © 2003 IEEE.