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20 GB/S referenceless quarter-rate PLL-based clock data recovery circuit in 130 NM CMOS technology
, Cumming D.R.S.
Published in
2008
Pages: 147 - 150
Abstract
This paper describes the design and transistor level simulation of a novel architecture of PLL-based clock and data recovery (PLL-CDR) circuit. The proposed PLL-CDR is a referenceless quarter-rate design that receives data at 20 Gb/s rate whereas its internal circuits work at 5 GHz frequency rate. This proposed architecture utilizes a quarterrate early-late type phase detector (ELPD), a quarter-rate digital quadricorrelator frequency detector (DQFD) and a quarter-rate ring type voltage-controlled oscillator (VCO). The simulation results at 20 Gb/s data rate show that the quarter-rate PLL-based CDR is a functional concept. The suggested chip design is realized in UMC 130 nm CMOS technology and occupies an area of 920μm × 315μm. The circuit's power dissipation excluding the output buffers is about 97 mW at a supply voltage of 1.2V according to the transistor level simulation results. Copyright © 2008 by Department of Microelectronics & Computer Science, Technical University of Lodz.
About the journal
JournalProceedings of The 15th International Conference Mixed Design of Integrated Circuits and Systems, MIXDES 2008
Open AccessNo