Abstract
In this paper, an efficient (in the AT and AT2 senses) systolic implementation of state-space realization of the IIR digital filters is presented. The technique used is based on block-state description in which the state update matrix is full. The new implementation has significantly reduced number of processor elements while simultaneously maintaining a high input sampling rate.
| Original language | English |
|---|---|
| Pages (from-to) | 267-270 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 4 |
| State | Published - 1994 |
| Externally published | Yes |
| Event | Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England Duration: 30 May 1994 → 2 Jun 1994 |
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