Systolic implementation of fixed-point state-space digital filter

An efficient (in the area × time sense) systolic implementation for Nth-order state-space IIR digital filters is presented. The number of processor elements involved in the implementation is linear with respect to the filter order. All double-precision operations are localised inside the processor units and efficiently executed using novel high-speed inner-product processors. The paths between the processor elements carry single-precision data which results in reducing the communication overhead. These features combine to improve area × time performance measure without any increase in the output roundoff noise. The proposed architecture renders the state-space structures of IIR digital filter more amendable to hardware implementations. A comparison in terms of computation delay and hardware area between the suggested architecture and non-systolic parallel architecture is presented. This comparison shows that the proposed implementation provides a better performance in the area × time sense over the fully parallel architecture.