Optimal placement for hierarchical VLSI layout design

An analytical technique to optimize the placement of functional blocks is presented. The placement problem is formulated as a constrained non-linear optimization problem. The mathematical formulation incorporates the dimensions of fixed-shaped blocks as well as the bounds on the aspect ratios of variable-shaped blocks. The overlaps are defined as constraints so that no overlapping takes place during the optimization process. Computer implementation of the proposed technique is described and results are presented.