Impact of technology scaling on the minimum energy point for FinFET based flip-flops

Osama Abdelkader; Hassan Mostafa; Hamdy Abdelhamid; Ahmed Soliman

doi:10.1109/ICECS.2015.7440348

Impact of technology scaling on the minimum energy point for FinFET based flip-flops

Osama Abdelkader
, Hassan Mostafa
, Hamdy Abdelhamid
, Ahmed Soliman

Siemens
Cairo University
Zewail City of Science and Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Analysis of FinFET based transmission gate (TG), sense amplifier (SA), and semi dynamic (SD) Flip-flops metrics are evaluated with technology scaling from 20nm down to 7nm technology node. The impact of supply voltage variation on delay, power, and energy is reported. The power delay product of Flip-flops is enhanced with technology scaling. The optimum supply voltage value at each technology node from minimum energy perspective is evaluated which is used by the industry to optimize logic and memory circuitry designs. For instance, considering the 7nm TG Flip-flop, the optimum supply voltage from energy saving point of view occurs at 0.65V. The work also characterizes each Flip-flop according to the obtained simulation results. SD Flip-flop has the best performance, however it exhibits high power consumption. TG Flip-flop is the best choice from power dissipation perspective, but it has high clock load. SA Flip-flop has a very useful feature of monotonous transitions at the outputs, which drives fast domino logic, however it might have glitches and it is the most vulnerable to soft errors.

Original language	English
Title of host publication	2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	462-465
Number of pages	4
ISBN (Electronic)	9781509002467
DOIs	https://doi.org/10.1109/ICECS.2015.7440348
State	Published - 23 Mar 2016
Externally published	Yes
Event	IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015 - Cairo, Egypt Duration: 6 Dec 2015 → 9 Dec 2015

Publication series

Name	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume	2016-March

Conference

Conference	IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015
Country/Territory	Egypt
City	Cairo
Period	6/12/15 → 9/12/15

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy
SDG 9 Industry, Innovation, and Infrastructure

Access to Document

10.1109/ICECS.2015.7440348

Cite this

Abdelkader, O., Mostafa, H., Abdelhamid, H., & Soliman, A. (2016). Impact of technology scaling on the minimum energy point for FinFET based flip-flops. In 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015 (pp. 462-465). Article 7440348 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 2016-March). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS.2015.7440348

Abdelkader, Osama ; Mostafa, Hassan ; Abdelhamid, Hamdy et al. / Impact of technology scaling on the minimum energy point for FinFET based flip-flops. 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 462-465 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).

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title = "Impact of technology scaling on the minimum energy point for FinFET based flip-flops",

abstract = "Analysis of FinFET based transmission gate (TG), sense amplifier (SA), and semi dynamic (SD) Flip-flops metrics are evaluated with technology scaling from 20nm down to 7nm technology node. The impact of supply voltage variation on delay, power, and energy is reported. The power delay product of Flip-flops is enhanced with technology scaling. The optimum supply voltage value at each technology node from minimum energy perspective is evaluated which is used by the industry to optimize logic and memory circuitry designs. For instance, considering the 7nm TG Flip-flop, the optimum supply voltage from energy saving point of view occurs at 0.65V. The work also characterizes each Flip-flop according to the obtained simulation results. SD Flip-flop has the best performance, however it exhibits high power consumption. TG Flip-flop is the best choice from power dissipation perspective, but it has high clock load. SA Flip-flop has a very useful feature of monotonous transitions at the outputs, which drives fast domino logic, however it might have glitches and it is the most vulnerable to soft errors.",

author = "Osama Abdelkader and Hassan Mostafa and Hamdy Abdelhamid and Ahmed Soliman",

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year = "2016",

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doi = "10.1109/ICECS.2015.7440348",

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Abdelkader, O, Mostafa, H, Abdelhamid, H & Soliman, A 2016, Impact of technology scaling on the minimum energy point for FinFET based flip-flops. in 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015., 7440348, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, vol. 2016-March, Institute of Electrical and Electronics Engineers Inc., pp. 462-465, IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015, Cairo, Egypt, 6/12/15. https://doi.org/10.1109/ICECS.2015.7440348

Impact of technology scaling on the minimum energy point for FinFET based flip-flops. / Abdelkader, Osama; Mostafa, Hassan; Abdelhamid, Hamdy et al.
2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015. Institute of Electrical and Electronics Engineers Inc., 2016. p. 462-465 7440348 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 2016-March).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Impact of technology scaling on the minimum energy point for FinFET based flip-flops

AU - Abdelkader, Osama

AU - Mostafa, Hassan

AU - Abdelhamid, Hamdy

AU - Soliman, Ahmed

PY - 2016/3/23

Y1 - 2016/3/23

N2 - Analysis of FinFET based transmission gate (TG), sense amplifier (SA), and semi dynamic (SD) Flip-flops metrics are evaluated with technology scaling from 20nm down to 7nm technology node. The impact of supply voltage variation on delay, power, and energy is reported. The power delay product of Flip-flops is enhanced with technology scaling. The optimum supply voltage value at each technology node from minimum energy perspective is evaluated which is used by the industry to optimize logic and memory circuitry designs. For instance, considering the 7nm TG Flip-flop, the optimum supply voltage from energy saving point of view occurs at 0.65V. The work also characterizes each Flip-flop according to the obtained simulation results. SD Flip-flop has the best performance, however it exhibits high power consumption. TG Flip-flop is the best choice from power dissipation perspective, but it has high clock load. SA Flip-flop has a very useful feature of monotonous transitions at the outputs, which drives fast domino logic, however it might have glitches and it is the most vulnerable to soft errors.

AB - Analysis of FinFET based transmission gate (TG), sense amplifier (SA), and semi dynamic (SD) Flip-flops metrics are evaluated with technology scaling from 20nm down to 7nm technology node. The impact of supply voltage variation on delay, power, and energy is reported. The power delay product of Flip-flops is enhanced with technology scaling. The optimum supply voltage value at each technology node from minimum energy perspective is evaluated which is used by the industry to optimize logic and memory circuitry designs. For instance, considering the 7nm TG Flip-flop, the optimum supply voltage from energy saving point of view occurs at 0.65V. The work also characterizes each Flip-flop according to the obtained simulation results. SD Flip-flop has the best performance, however it exhibits high power consumption. TG Flip-flop is the best choice from power dissipation perspective, but it has high clock load. SA Flip-flop has a very useful feature of monotonous transitions at the outputs, which drives fast domino logic, however it might have glitches and it is the most vulnerable to soft errors.

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T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

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BT - 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015

Y2 - 6 December 2015 through 9 December 2015

ER -

Abdelkader O, Mostafa H, Abdelhamid H, Soliman A. Impact of technology scaling on the minimum energy point for FinFET based flip-flops. In 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015. Institute of Electrical and Electronics Engineers Inc. 2016. p. 462-465. 7440348. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). doi: 10.1109/ICECS.2015.7440348

Impact of technology scaling on the minimum energy point for FinFET based flip-flops

Abstract

Publication series

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UN SDGs

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