Impact of Bottom Dielectric Isolation of Si-Stacked Nanosheet Transistor on Stress and Self-Heating at 3-nm Node and Beyond

This study examines the effect of leakage current reduction techniques on the performance of the nanosheet FETs (NS-FETs) at 3 nm and beyond. We study the effects of the punchthrough stopper (PTS) and bottom dielectric isolation (BDI) schemes on stress and self-heating. We have developed a new simulation flow based on quantum correction of Monte Carlo (MC) simulation and calibration of drift diffusion model. We calibrate the simulation results with the latest available published experimental data. BDI was found to lower the average channel stress by 85% and reduced drive current compared with PTS with ideal source/drain (S/D) stressors. The impact of nonideal, defective S/D stressors on the development of channel stress of PTS is also covered in this article. We also found that the BDI structure raises the lattice temperature dramatically compared with the PTS structure at the same dc bias current level. The performance of the BDI structure is improved by introducing metal S/D to increase the contact area between M0 and S/D epi, leading to a significant improvement in lattice temperature, drive current, and RC delay up to 30%.