TY - GEN
T1 - FPGA implementation of a simple approach for jitter minimisation in Ethernet for real-time control communication
AU - Ishak, Mohamad Khairi
AU - Herrmann, Guido
AU - Pearson, Martin
PY - 2012
Y1 - 2012
N2 - An approach for cheap and deterministic control communication using Ethernet real-time control communication is presented. Field-programmable gate array (FPGA) technology, i.e Xilinx XC3S500E from the Spartan-3E family, is used to implement the Ethernet communication strategy. The unit is defined in Verilog using Xilinx ISE 11.1 software tools. Data packages are sent at well defined times to avoid collisions. Collisions mainly occur due to jitter of the transmitter system, so that arbitration (similar to CANopen) is necessary. The Binary Exponential Backoff (BEB) scheme is used. This paper analyzes and investigates how the backoff time affects the performance of the Carrier Sense Multiple Access protocol with Collision Detection (CSMA/CD) in a basic Media Access Controller (MAC), in terms of data arrival characteristics, i.e jitter and delay. We propose to assign different minimal backoff times for each of the CSMA/CD controller units to minimize packet collisions. The proposed hardware design shows the advantage of our approach over a standard CSMA/CD setting.
AB - An approach for cheap and deterministic control communication using Ethernet real-time control communication is presented. Field-programmable gate array (FPGA) technology, i.e Xilinx XC3S500E from the Spartan-3E family, is used to implement the Ethernet communication strategy. The unit is defined in Verilog using Xilinx ISE 11.1 software tools. Data packages are sent at well defined times to avoid collisions. Collisions mainly occur due to jitter of the transmitter system, so that arbitration (similar to CANopen) is necessary. The Binary Exponential Backoff (BEB) scheme is used. This paper analyzes and investigates how the backoff time affects the performance of the Carrier Sense Multiple Access protocol with Collision Detection (CSMA/CD) in a basic Media Access Controller (MAC), in terms of data arrival characteristics, i.e jitter and delay. We propose to assign different minimal backoff times for each of the CSMA/CD controller units to minimize packet collisions. The proposed hardware design shows the advantage of our approach over a standard CSMA/CD setting.
KW - Binary Exponential Backoff
KW - CSMA/CD
KW - Ethernet
KW - network model
UR - https://www.scopus.com/pages/publications/84870406120
U2 - 10.1109/HPCC.2012.197
DO - 10.1109/HPCC.2012.197
M3 - Conference contribution
AN - SCOPUS:84870406120
SN - 9780769547497
T3 - Proceedings of the 14th IEEE International Conference on High Performance Computing and Communications, HPCC-2012 - 9th IEEE International Conference on Embedded Software and Systems, ICESS-2012
SP - 1337
EP - 1343
BT - Proceedings of the 14th IEEE International Conference on High Performance Computing and Communications, HPCC-2012 - 9th IEEE International Conference on Embedded Software and Systems, ICESS-2012
T2 - 14th IEEE International Conference on High Performance Computing and Communications, HPCC-2012 - 9th IEEE International Conference on Embedded Software and Systems, ICESS-2012
Y2 - 25 June 2012 through 27 June 2012
ER -