Digital and analog/RF performance of stacked nanosheet transistors with various source/drain contact and bottom isolation designs

We present a study of the digital and analog/RF performances of nanosheet field-effect transistors (NSFETs) for different source–drain (S/D) and bottom isolation configurations. The bottom isolation techniques evaluated include the punch-through stopper (PTS) and bottom dielectric isolation (BDI). Regarding S/D contact methodologies, three configurations were examined: top, wrapped-around (WAC), and metal sidewall (MSW). The combination of bottom isolation techniques and S/D configurations led to eight device variants. For each structural variation, the parasitic components are extracted, and the circuit performance is evaluated. For each structure, the digital circuit performance is evaluated by investigating the delay of a CMOS inverter. The RF performance was also assessed by investigating the cutoff frequency (F_t), the maximum frequency of oscillation (F), and the RF parameters for each structure considering the back-end of line (BEOL) parasitics. The BDI scheme demonstrated improved performance over the conventional PTS by an average of 5% and 9% for digital and RF applications, respectively. Combining BDI with MSW and WAC schemes significantly enhances the performance. For instance, the maximum performance gain over conventional PTS and top-contact schemes was 32% for digital applications, while F_t improved by 8% and F improved by 13%. MSW outperformed WAC by an average of 2%.