CMOS IC design and verilog-a modelling of 10-Gb/s PLL-based deserializer for inter-chip communication in SOC

Maher Assaad; David R.S. Cumming

doi:10.1109/ISSOC.2007.4427420

CMOS IC design and verilog-a modelling of 10-Gb/s PLL-based deserializer for inter-chip communication in SOC

Maher Assaad
, David R.S. Cumming

University of Glasgow

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

The results of design and simulation of a novel architecture for a 1.0 Gb/s PLL-based clock and data recovery (CDR) circuit are presented. The proposed PLL-based CDR is a referenceless quarter-rate design and can be used in a deserializer as part of the Serializer/Deserializer (SERDES) device usually utilized in inter-chip communication networks. This CDR circuit is designed in a standard 0.13 um CMOS technology, modelled using the Verilog-A language and simulated in SPECTRE in order to verify its functionality in an eight input SERDES based chip-to-chip communication system.

Original language	English
Title of host publication	2007 International Symposium on System-on-Chip Proceedings, SOC
DOIs	https://doi.org/10.1109/ISSOC.2007.4427420
State	Published - 2007
Externally published	Yes
Event	2007 International Symposium on System-on-Chip, SOC - Tampere, Finland Duration: 20 Nov 2007 → 21 Nov 2007

Publication series

Name	2007 International Symposium on System-on-Chip Proceedings, SOC

Conference

Conference	2007 International Symposium on System-on-Chip, SOC
Country/Territory	Finland
City	Tampere
Period	20/11/07 → 21/11/07

Access to Document

10.1109/ISSOC.2007.4427420

Cite this

@inproceedings{7b2d2c39261447c1a4b575b192b65a3e,

title = "CMOS IC design and verilog-a modelling of 10-Gb/s PLL-based deserializer for inter-chip communication in SOC",

abstract = "The results of design and simulation of a novel architecture for a 1.0 Gb/s PLL-based clock and data recovery (CDR) circuit are presented. The proposed PLL-based CDR is a referenceless quarter-rate design and can be used in a deserializer as part of the Serializer/Deserializer (SERDES) device usually utilized in inter-chip communication networks. This CDR circuit is designed in a standard 0.13 um CMOS technology, modelled using the Verilog-A language and simulated in SPECTRE in order to verify its functionality in an eight input SERDES based chip-to-chip communication system.",

author = "Maher Assaad and Cumming, \{David R.S.\}",

year = "2007",

doi = "10.1109/ISSOC.2007.4427420",

language = "English",

isbn = "1424413672",

series = "2007 International Symposium on System-on-Chip Proceedings, SOC",

booktitle = "2007 International Symposium on System-on-Chip Proceedings, SOC",

note = "2007 International Symposium on System-on-Chip, SOC ; Conference date: 20-11-2007 Through 21-11-2007",

}

Assaad, M & Cumming, DRS 2007, CMOS IC design and verilog-a modelling of 10-Gb/s PLL-based deserializer for inter-chip communication in SOC. in 2007 International Symposium on System-on-Chip Proceedings, SOC., 4427420, 2007 International Symposium on System-on-Chip Proceedings, SOC, 2007 International Symposium on System-on-Chip, SOC, Tampere, Finland, 20/11/07. https://doi.org/10.1109/ISSOC.2007.4427420

CMOS IC design and verilog-a modelling of 10-Gb/s PLL-based deserializer for inter-chip communication in SOC. / Assaad, Maher; Cumming, David R.S.
2007 International Symposium on System-on-Chip Proceedings, SOC. 2007. 4427420 (2007 International Symposium on System-on-Chip Proceedings, SOC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - CMOS IC design and verilog-a modelling of 10-Gb/s PLL-based deserializer for inter-chip communication in SOC

AU - Assaad, Maher

AU - Cumming, David R.S.

PY - 2007

Y1 - 2007

N2 - The results of design and simulation of a novel architecture for a 1.0 Gb/s PLL-based clock and data recovery (CDR) circuit are presented. The proposed PLL-based CDR is a referenceless quarter-rate design and can be used in a deserializer as part of the Serializer/Deserializer (SERDES) device usually utilized in inter-chip communication networks. This CDR circuit is designed in a standard 0.13 um CMOS technology, modelled using the Verilog-A language and simulated in SPECTRE in order to verify its functionality in an eight input SERDES based chip-to-chip communication system.

AB - The results of design and simulation of a novel architecture for a 1.0 Gb/s PLL-based clock and data recovery (CDR) circuit are presented. The proposed PLL-based CDR is a referenceless quarter-rate design and can be used in a deserializer as part of the Serializer/Deserializer (SERDES) device usually utilized in inter-chip communication networks. This CDR circuit is designed in a standard 0.13 um CMOS technology, modelled using the Verilog-A language and simulated in SPECTRE in order to verify its functionality in an eight input SERDES based chip-to-chip communication system.

UR - https://www.scopus.com/pages/publications/48049117329

U2 - 10.1109/ISSOC.2007.4427420

DO - 10.1109/ISSOC.2007.4427420

M3 - Conference contribution

AN - SCOPUS:48049117329

SN - 1424413672

SN - 9781424413676

T3 - 2007 International Symposium on System-on-Chip Proceedings, SOC

BT - 2007 International Symposium on System-on-Chip Proceedings, SOC

T2 - 2007 International Symposium on System-on-Chip, SOC

Y2 - 20 November 2007 through 21 November 2007

ER -

CMOS IC design and verilog-a modelling of 10-Gb/s PLL-based deserializer for inter-chip communication in SOC

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