An FPGA-based design and implementation of an all-digital serializer for inter module communication in SoC

In this paper, an all-digital serializer circuit based on a novel frequency and delay locked-loop (F/DLL) clock multiplier is presented. The advantages of the proposed F/DLL are that, it simultaneously generates a high frequency signal from a low frequency reference signal and synchronizes the two signals without jitter accumulation issue. Moreover, it can be easily adapted for different FPGA families as well as implemented as an integrated circuit. The proposed serializer circuit is used as a part of a SERDES in inter-module communication in system-on-chip (SoC). The simulation and experimental results confirm the performance of the serializer with the proposed clock multiplier.