An algorithm for polygon conversion to boxes for VLSI layouts

A. J. Al-Khalili; D. Al-Khalili; K. Ammar

doi:10.1016/0167-9260(88)90004-1

An algorithm for polygon conversion to boxes for VLSI layouts

A. J. Al-Khalili
, D. Al-Khalili
, K. Ammar

Concordia University
Royal Military College of Canada

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

We develop an algorithm for covering polygons by rectangles. The algorithm achieves a minimum number of rectangles in most cases and in a short time. The algorithm is suitable for use in generating masks for microcircuits, design rule checking of VLSI layouts, graphical editors, etc.

Original language	English
Pages (from-to)	291-308
Number of pages	18
Journal	Integration
Volume	6
Issue number	3
DOIs	https://doi.org/10.1016/0167-9260(88)90004-1
State	Published - Sep 1988
Externally published	Yes

Keywords

CAD of VLSI layout
Rectilinear polygons
figure description
graphical editing
minimal description
polygon coverage

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10.1016/0167-9260(88)90004-1

Cite this

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title = "An algorithm for polygon conversion to boxes for VLSI layouts",

abstract = "We develop an algorithm for covering polygons by rectangles. The algorithm achieves a minimum number of rectangles in most cases and in a short time. The algorithm is suitable for use in generating masks for microcircuits, design rule checking of VLSI layouts, graphical editors, etc.",

keywords = "CAD of VLSI layout, Rectilinear polygons, figure description, graphical editing, minimal description, polygon coverage",

author = "Al-Khalili, \{A. J.\} and D. Al-Khalili and K. Ammar",

year = "1988",

month = sep,

doi = "10.1016/0167-9260(88)90004-1",

language = "English",

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T1 - An algorithm for polygon conversion to boxes for VLSI layouts

AU - Al-Khalili, A. J.

AU - Al-Khalili, D.

AU - Ammar, K.

PY - 1988/9

Y1 - 1988/9

N2 - We develop an algorithm for covering polygons by rectangles. The algorithm achieves a minimum number of rectangles in most cases and in a short time. The algorithm is suitable for use in generating masks for microcircuits, design rule checking of VLSI layouts, graphical editors, etc.

AB - We develop an algorithm for covering polygons by rectangles. The algorithm achieves a minimum number of rectangles in most cases and in a short time. The algorithm is suitable for use in generating masks for microcircuits, design rule checking of VLSI layouts, graphical editors, etc.

KW - CAD of VLSI layout

KW - Rectilinear polygons

KW - figure description

KW - graphical editing

KW - minimal description

KW - polygon coverage

UR - https://www.scopus.com/pages/publications/0024071550

U2 - 10.1016/0167-9260(88)90004-1

DO - 10.1016/0167-9260(88)90004-1

M3 - Article

AN - SCOPUS:0024071550

SN - 0167-9260

VL - 6

SP - 291

EP - 308

JO - Integration

JF - Integration

IS - 3

ER -

An algorithm for polygon conversion to boxes for VLSI layouts

Abstract

Keywords

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