TY - GEN
T1 - A synthesizable serial link for point-to-point communication in SoC/NoC
AU - Assaad, Maher
AU - Harb, Adnan
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2018/1/24
Y1 - 2018/1/24
N2 - This paper presents an only hardware description language (HDL)-based serial link (SerDes) design that has been synthesized on Altera DE2-70 FPGA board as a quick proof of concept for validation purpose. Though some blocks are adopted from their analog counterpart however the entire architecture has been implemented using the Verilog language, hence requires no analog or off-chip components and exhibit better power efficiency and jitter but lower data rate. Furthermore, being an HDL-based design makes it easy to implement as an IC and suitable for certain applications such as multicore and NoC architectures. Key circuit blocks include a built-in PRBS generator for testing purpose, a clock generation circuit, and a quarter-rate clock and data recovery (CDR) circuit. Including FPGA's peripherals, the proposed link achieves a power efficiency of 5.79 pW/b/s and a bit error rate (BER) lower than 10-12, and operates continuously over the range of 167.32 Mb/s to 193.6 Mb/s.
AB - This paper presents an only hardware description language (HDL)-based serial link (SerDes) design that has been synthesized on Altera DE2-70 FPGA board as a quick proof of concept for validation purpose. Though some blocks are adopted from their analog counterpart however the entire architecture has been implemented using the Verilog language, hence requires no analog or off-chip components and exhibit better power efficiency and jitter but lower data rate. Furthermore, being an HDL-based design makes it easy to implement as an IC and suitable for certain applications such as multicore and NoC architectures. Key circuit blocks include a built-in PRBS generator for testing purpose, a clock generation circuit, and a quarter-rate clock and data recovery (CDR) circuit. Including FPGA's peripherals, the proposed link achieves a power efficiency of 5.79 pW/b/s and a bit error rate (BER) lower than 10-12, and operates continuously over the range of 167.32 Mb/s to 193.6 Mb/s.
KW - Low-power serial link
KW - Quarter-rate clock and data recovery (CDR)
KW - Serializer/deserializer (SerDes)
UR - https://www.scopus.com/pages/publications/85045148275
U2 - 10.1109/ICM.2017.8268824
DO - 10.1109/ICM.2017.8268824
M3 - Conference contribution
AN - SCOPUS:85045148275
T3 - Proceedings of the International Conference on Microelectronics, ICM
SP - 1
EP - 4
BT - 2017 29th International Conference on Microelectronics, ICM 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 29th International Conference on Microelectronics, ICM 2017
Y2 - 10 December 2017 through 13 December 2017
ER -