A hardware description language-based serial link for multicores SoC/NoC interconnect

This paper presents an only hardware description language (HDL)-based serial communication link design that has been synthesized on an Altera Cyclone II as a quick proof of concept for validation purpose. Though some blocks are adopted from their analog counterparts, however the entire architecture has been implemented using the Verilog language, hence requires no analog or off-chip components and exhibits better power efficiency and jitter performance. Despite that fact that the proposed solution is slower than the analog CML design, it is re-programmable and can be synthesized and implemented as an IC and therefore suitable for certain applications where no analog components are permitted such as Network on Chip (NoC) or multi-processors SoC (MPSoC). The full-rate link achieves a power efficiency of 5.88 pW/b/s with a normalized peakto-peak jitter of the recovered clock of 5.48%, whereas quarter-rate architecture achieves power efficiency of 5.12 pW/b/s and normalized peak-to-peak jitter of the recovered clock of 0.45%. The operation of the proposed serial link has been experimentally demonstrated by using it as a medium of transmitting/receiving static images.