A 2D compact model for lightly doped DG MOSFETs (P-DGFETs) including negative bias temperature instability (NBTI) and short channel effects (SCEs)

In this paper, a 2D compact model for potential and threshold voltage for lightly doped symmetrical double gate (DG) p-channel MOSFETs (PMOS) including negative bias temperature instability (NBTI) and short channel effects (SCEs) is presented. The model is dedicated to nano scale MOSFETs below 30 nm. In this model, both effects of interface state generation and hole-trapping are considered. Moreover, the effects of scaling down the oxide thickness and the channel thickness on NBTI are discussed. Our model is matched very well with numerical simulations obtained from COMSOL multi-physics at different drain voltages (V_d). A 4% shift in threshold voltage roll-off and 47% shift in drain induced barrier lowering (DIBL) is achieved at a gate length of 10 nm after 10 years of operation at a frequency of 1 GHz.